Sequential logic synthesis and formal verification
ABC is a growing software system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. ABC combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification. ABC provides an experimental implementation of these algorithms and a programming environment for building similar applications. Future development will focus on improving the algorithms and making most of the packages stand-alone. This will allow the user to customize ABC for their needs as if it were a toolbox rather than a complete tool.
Release | Stable | Testing |
---|---|---|
Fedora Rawhide | 0.41-1.20240524git237d813.fc41 | - |
Fedora 40 | 0.41-1.20240524git237d813.fc40 | 0.39-1.20240314git0cd90d0.fc40 |
Fedora 39 | 0.39-1.20240314git0cd90d0.fc39 | - |
Fedora 38 | 0.39-1.20240314git0cd90d0.fc38 | - |
You can contact the maintainers of this package via email at
yosyshq-abc dash maintainers at fedoraproject dot org
.